High Speed Architectures for Finding the First two Maximum/Minimum Values
نویسندگان
چکیده
منابع مشابه
Reduced Complexity MS Algorithm for Finding the First Two Minima in Tree Architectures
High speed architectures for finding the first two max/min values are of paramount importance in several applications, including iterative decoders and for proposed the adder and Low density parity check code (LDPC) has been implemented. The min-sum processing that it produces only two different output magnitude values irrespective of the number of incoming bit-to check messages. The new microa...
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ژورنال
عنوان ژورنال: IEEE Transactions on Very Large Scale Integration (VLSI) Systems
سال: 2012
ISSN: 1063-8210,1557-9999
DOI: 10.1109/tvlsi.2011.2174166